The present invention relates to a digital counter, and to a reset technique therefor. The invention is especially, but not exclusively, suitable for a ripple counter. The invention is also especially, but not exclusively, suitable for incorporation in an integrated circuit.
FIG. 1 shows schematically the principle of a self-looping ripple counter 10. The counter 10 comprises a plurality of flip-flop counter stages each arranged with an inverted output fed back to an input. The first stage 12a toggles on each input clock cycle. Each subsequent counter stage 12 toggles at half the rate of the preceding stage. Modulo-N detection circuitry 14 monitors the count value in the plural stages, and generates a reset signal 16 when the count value has reached a predetermined maximum (which typically might not be a power of 2). The reset signal 16 is applied in parallel to reset circuitry 18 built in to each flip-flop 12, to force the flip-flop to a certain state, typically zero.
A disadvantage with the above type of circuit is that the reset circuitry 18 in each flip-flop 12 slows the maximum rate at which the flip-flop can toggle. Typically the reset circuitry comprises one or more semiconductor devices, which add capacitance to the circuit. In some situations, speed is not important. However, modern designs place an ever increasing importance on obtaining increased speed at minimum power consumption, which often means operating circuitry at its limit.
For example, using 0.18 micron CMOS integrated circuit technology, the theoretical maximum clocking speed of a flip-flop, for a particular logic family operating within a required power consumption level, might be about 1 GHz. However, in practice, the reset circuitry 18 typically reduces this speed by 20% to about 800 MHz. Therefore, more power demanding circuits have to be used for speeds above 800 MHz.
In a ripple counter, the toggle speed of flip-flop 12 places two limitations on the circuit 10. Firstly, it limits the maximum counting rate of the circuit by the physical speed at which the first flip-flop 12a can toggle, since the first flip-flop 12a operates at the highest rate. Secondly, it limits the counting speed by causing propagation delay through the plural flip-flops 12, and delaying the stable count value. It will be appreciated that the modulo-N detection circuit 14 requires a stable count value to detect the occurrence of the predetermined maximum. If another count input arrives at the first flip-flop 12a before the previous count value has xe2x80x9crippledxe2x80x9d through the last flip-flop, then the count value will not be stable for detection. This second problem is more serious for long ripple counters containing many stages flip-flops 12.
Finally, a further disadvantage with current reset circuits 18 is that they are level-driven, rather than edge-driven. The reset signal 16 therefore has to be applied and held for at least a certain minimum duration to achieve the reset, during which time the flip-flops 12 cannot toggle. This places a further time limitation on the maximum continuous counting rate of the circuit 10. This also limits the ability of the circuit 10 to count for a predetermined time following the occurrence of the count value causing the circuit 10 to reset.
The invention relates to a counter stage which may comprise a flip-flop and a reset circuit. The flip-flop may be configured to toggle a flip-flop signal between a first and a second state in response to a count signal applied to a clock input to effect a counting operation. The reset circuit may be configured to reset the counter stage to a predetermined state without changing the state of the flip-flop signal.
The objects, features and advantages of the invention include one or more of: (i) increasing the toggling speed of the count stage flip-flop by removing a reset circuit from the counting loop of the flip-flop; (ii) reducing the time required to reset a stage; and/or (iii) increasing the maximum count speed of a ripple counter. Other objects, features and advantages will become more apparent from the description, claims and drawings.